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  • VSM Models

    SPI Protocol Analyser

    The Proteus VSM SPI/Microwire Protocol Analyser provides an industrial strength virtual instrument for testing, debugging and monitoring SPI/microwire communications.The analyser has two purposes: to allow you to view data sent along the SPI lines and to permit you to transmit data either as a master or as a slave device. This makes it invaluable both as a debugging instrument but also as a development and testing aid when writing your own routines (not to mention being a fraction of the cost of it's hardware equivalent). Simply place and wire onto the appropriate lines in your Proteus VSM schematic and run the simulation.

    Features

    The main features of the SPI Protocol Analyser are:

    • Fully mode configurable:

      The protocol analyser can act as an master or slave device or simply be used to monitor traffic on the bus.
    • Live data capture and display:

      Activity is shown on the analyser display as it happens.
    • High resolution timing:

      Timing is shown both at byte and bit level and the accuracy of the timing display is user configurable up to 10 decimal places.
    • Activity Indication:

      The analyser detects and displays when the SS Pin is active.
    • High granularity analysis:

      The display allows you to drill down both to byte and to bit levels, providing timing information, logic levels and data at each level.
    • Error Detection:

      When partial data is received or unexpected logic levels are detected the display will clearly indicate the problem (down to bit levels).
    • Sequence entry and bus stimulus:

      You can enter sequences of data (either as a Master or Slave device) and send them on the bus. This is both an major timesaver (if your microcontroller is a slave device and you want to test your implementation for example) and an excellent debugging tool. Specified sequences can be stored and autoloaded between simulation sessions.
    • Large Sampling Capabilities:

      The amount of captured data is a FIFO buffer defaulted to 1000 complete sequences.
    • System Level Synchronised:

      The unique nature of Proteus VSM means that pausing during a simulation run with pause the entire system (including microcontroller clocks, generators etc.). This allows you to study bus activity at the point it happens, even to the level of single stepping your microcontroller code and watching the signals propogate onto the bus.

    The SPI Protocol Analyser is currently included as standard with all Proteus VSM microcontroller simulation packages.

    The SPI Protocol Analyser monitoring the bus on the Microchip™ MCP4922 Demo schematic.