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  • ProSPICE - Advanced Simulation Features

    The Advanced Simulation Option can be added to all Proteus PCB Design and Proteus VSM products including the Starter Kit. It extends the functionality of the basic simulator to provide a full range of graph-based analyses. Graph based simulation is akin to conventional SPICE simulation where you first draw the circuit, set-up source generators, select points to be monitored and then run the simulator. When the simulation is complete the results are displayed and you analyse these at your leisure. The Proteus Design Suite with the Advanced Simulation Features module makes this as effortless as possible.

    Product Summary

    Advanced Simulation Features Module Enables:

    Analogue Transient Analysis.

    Distortion Analysis

    Digital Transient Analysis.

    Transfer Curve Analysis

    Mixed Mode Transient Analysis

    DC Parameter Sweep Analysis

    Frequency Analysis.

    AC Parameter Sweep and Operating Point

    Fourier Analysis.

    Digital Conformance Analysis

    Noise Analysis.

    Interactive Analysis.

    Labcenter EasyHDL Scripting Language

    Purchasing Options

    The Advanced Simulation Features integrates completely with all of our Proteus PCB Design packages, enabling the important verification stage of the project design lifecycle.

    The functionality enabled by Advanced Simulation Features also provides an ideal complement to our renowned Proteus VSM micro-controller simulation packages.

    Product Features

    Advanced Simulation Features Module Functionality:

    • The full functionality of the simulation core and the features in the Basic Simulation Package.
    • Use of the Labcenter EasyHDL scripting language to define arbitrary signal chains via scriptable generators.
    • Graph based simulation of all the aforementioned analyses types.
    • Graphs display analogue, digital and bus data. Frequency plots show gain and phase in dB or linear measurements..
    • Audio Analysis computes a waveform and plays it to your sound-card. Results can be exported as a *.wav file (and later imported via the audio generator if required).
    • Interactive Analysis runs an interactive simulation and captures the results onto a graph.
    • Digital Conformance analysis - see below for details of this powerful Quality Assurance tool.
    • Probe expressions allow plotting of mathematical functions derived from measured voltage and currents.
    • Take accurate measurements using graph cursors.
    • Export simulation results to other software (e.g. Excel) in CSV format.

    Basic Operation

    PWLIN Generator

    Piecewise Linear Generator Type.

    Having drawn the schematic, you choose the type of circuit analysis you require (transient, frequency, noise, etc.) by placing a Graph of the appropriate type on the schematic. You can place as many graphs as you want and can even have several graphs of the same type if you wish. Graph types supported include: Analogue, Digital and Mixed transient graphs as well as Frequency, Transfer, Noise, Distortion, Fourier, AC Sweep and DC Sweep and Audio graphs. The latter can be used to not only capture and display transient data but to also play it through a sound card.

    Next, add and configure Generators to stimulate the circuit and Probes at points to be monitored. These can be dragged and dropped on the schematic like any other component and can also be reconfigured or dragged about between simulations. Analogue generators available include DC, Sine, Pulse, Piecewise Linear, File, Audio, Exponent and Single Frequency FM types and digital generators available include Edge, Pulse, Clock and Pattern types.

    Scriptable Generator

    RS232 Serial Generator Data Scripted using EasyHDL.

    Alternatively, you can write your own use script using Labcenter's EasyHDL (a BASIC like language) for greater control and flexibility over the injected signals. EasyHDL is a programming language which can be used to write scripts for testing complex test signals. We have christened this language EasyHDL as it is much simpler to learn and use than general purpose hardware description languages such as Verilog or VHDL. However, not withstanding its relative simplicity, EasyHDL can be used to generate both analogue and digital waveforms, and it can be used to create complex test vectors in which one script specifies the behaviour of multiple generator objects on the schematic. Another major benefit is that the scripts themselves can be debugged (breakpoints, single stepping, variables etc.) during simulation.

    Finally you drag-and-drop one or more generators or probes on to a graph to choose what traces are displayed. A graph of a particular type with a given set of probes and generators is sufficient to tell ISIS and ProSPICE what part of the circuit to simulate, and what type of analysis to perform.

    Post simulation you can maximise any graph, zoom in or out on the data as well as take timing, voltage and other measurements.

    Analysis types available with the ProSpice Advanced Simulation option.

    Conformance Analysis - A Unique Quality Assurance Tool

    A conformance analysis compares one set of digital simulation results against another. The idea is that a design that has been previously accepted as working can be quickly re-tested after modification in order to prove that there have been no unwanted side effects arising from the change. This is particularly relevant in micro-controller based applications where the entire firmware program may need to be re-tested after changes have been made to the source code.

    Conformance or non-conformance is determined by comparing the test and reference results at each edge of the first trace on the graph. Very significantly, there is no requirement for the edges in the test and reference copies of this control trace to occur at the same times. This means that changes in the absolute timing of events within the results data do not necessarily imply conformance. This is particularly relevent in micro-controller applications where any changes to the code will be bound to effect the absolute timing of events within the system. In such cases, the control trace may be generated by the code itself on entry and/or exit to the routines under test.

    Conformance test of the PIC16 CCP1 module

    Conformance test of the PIC16 CCP1 module. The control trace's edges (CCP1 CLK, in yellow) define times at which the PWM output must be high and low. This is one of many tests we re-run each time we modify the PIC16 CPU model.